Spatial locality refers to the problem that once a location is referenced
- it will not be referenced again
- it will be referenced again
- a nearby location will be referenced soon
- none of the above
Answer - (3) a nearby location will be referenced soon
A polled interrupt is handled by
- software
- hardware
- firmware
- none of these
Answer - (1) software
Consider the following register-transfer language
R3 <-- R3 + M[R1 + R2]
where R1, R2 are the CPU registers and M is a memory location in primary memory. which addressing mode is suitable for the above register-transfer language?
- immediate
- indexed
- direct
- displacement
Answer - (2) indexed
Which memory unit has the lowest access time?
- cache
- registers
- magnetic disk
- main memory
Answer - (2) registers
The computer performs all mathematical and logical operations inside its
- memory unit
- central processing unit
- output unit
- visual display unit
Answer - (2) central processing unit
Which of the following are examples of input devices?
- visual display unit, dot matrix printer, laser printer
- keyboard, mouse, optical mark reader
- arithmetic and logic unit, the control unit
- RAM, ROM, PROM
Answer - (2) Keyboard, mouse, optical mark reader
In a 16-bit instruction code format 3-bit operation code, 12-bit address, and 1 bit is assigned for address mode designation. For indirect addressing, the mode bit is
- 0
- 1
- pointer
- off-set
Answer - (2) 1
What do CISC and RISC mean?
- common instruction set controller and rare instruction set controller
- complex instruction set controller and reduced instruction set controller
- compiled instruction set source code and recompiled instruction source code
- none of the above
Answer - (4) None of the above
During DMA transfer. DMA controller takes over the buses to manage the transfer
- directly from CPU to memory
- directly from memory to CPU
- indirectly between the I/O device and memory
- directly between the I/O device and memory
Answer - (4) directly between the I/O device and memory
Booth's algorithm is used in floating-point
- addition
- subtraction
- multiplication
- division
Answer - (3) multiplication
Match List-I with List-II and select the correct answer using the codes given below the lists:
List-I | Lis-II |
---|---|
A. Regs[R4] ← Regs[R4] + Regs[R3] | 1. immediate |
B. Regs[R4] ← Regs[R4] + 3 | 2. register |
C. Regs[R4] ← Regs[R4] + Mem[Regs[R1]] | 3. displacement |
A B C
- 3 2 1
- 2 1 3
- 1 2 3
- 3 1 2
Answer - (2) 2 1 3
A 32-bit address bus allows access to a memory of capacity
- 64 MB
- 16 MB
- 1 GB
- 4 GB
Answer - (4) 4 GB
Pipelining improves CPU performance due to
- reduced memory access time
- increased clock speed
- the introduction of parallelism
- additional functional units
Answer - (3) the introduction of parallelism
The system bus is made up of
- data bus
- data bus and address bus
- data bus and control bus
- the data bus, control bus, and address bus
Answer - (4) the data bus, control bus, and address bus
Cache memory enhances
- memory capacity
- memory access time
- effective memory access time
- secondary storage access time
Answer - (3) effective memory access time
Cache memory
- has greater capacity than RAM
- is faster to access than CPU registers
- is permanent storage
- faster to access than RAM
Answer - (4) faster to access than RAM
An instruction cycle refers to
- fetching an instruction
- clock speed
- fetching, decoding, and executing an instruction
- executing an instruction
Answer - (3) fetching, decoding, and executing an instruction
Given a 5 stage pipeline with stages taking 1, 2, 3, 1, 1 unit of time, the clock period of the pipeline is
- 8
- 1/8
- 1/3
- 3
Answer - (4) 3
A hardware interrupt is
- also called an internal interrupt
- also called an external interrupt
- an I/O interrupt
- a clock interrupt
Answer - (2) also called an external interrupt
The read/write line
- belongs to the data bus
- belongs to the control bus
- belongs to the address bus
- CPU bus
Answer - (2) belongs to the control bus
Note - more questions and answers will be added from time to time.
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